• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to an asynchronous data transmitting / receiving apparatus which reduces the memory area by reducing the capacity of a memory. The present invention relates to a first and second FIFO memory unit used for input and output of data to be transmitted and received, and the first and second FIFO memories are full. Multiplexing an address counter signal of a selected FIFO memory section to be selected and used, a first and second FIFO controller selection section for countering and outputting an address relating to data transmission or reception, and the first FIFO controller selection section in a data reception mode; And a first multiplexing / decoding unit for decoding and outputting the first FIFO memory and a second multiplexing / decoding unit for multiplexing and decoding the address counter signal of the second FIFO controller selection unit in a data transmission mode and outputting the same to the second FIFO memory. And the write / determine mode when the selected FIFO memory unit is used to determine whether to transmit or receive. A first multiplex transmission / reception selector for outputting an address counter signal, and a third multiplexer / decoder for multiplexing and decoding address counter signals related to reading / writing of the first / second transmission / reception selection unit and outputting the multiplexing / decoding unit to a selected FIFO memory unit; It is configured to include.
    公开号:KR19980059896A
    申请号:KR1019960079242
    申请日:1996-12-31
    公开日:1998-10-07
    发明作者:양두식
    申请人:문정환；엘지반도체 주식회사；
    IPC主号:
    专利说明:

    Asynchronous Data Transceiver
    The present invention relates to a data transmission and reception apparatus, and more particularly, to an asynchronous data transmission and reception apparatus having a reduced chip area by reducing a memory capacity.
    In general, in configuring a system, most modules employ a CPU to process work independently. A synchronous method of synchronizing a data processing clock to exchange data between modules, or an asynchronous processing of data asynchronously. Use the method.
    The synchronous method requires a lot of additional circuits in the system in order to synchronize between both modules and has a disadvantage of slowing down the processing speed of the system.
    In contrast, the asynchronous method is advantageous in terms of speed and price since the reading module and the writing module use separate input / output buffers.
    Hereinafter, with reference to the accompanying drawings will be described with respect to the asynchronous transmission and reception apparatus of the prior art.
    1 is a block diagram of a FIFO memory of a UART that does not support infrared communication of the prior art, Figure 2 is a block diagram of a FIFO memory of a UART supporting 4Mbps infrared communication of the prior art.
    Infrared communication, for example, refers to the use of infrared light to send and receive data between PCs located in close proximity.
    The Universal Asynchronous Receiver Transmitter (UART), which does not support infrared communication, supports a full duplex mode that can simultaneously function as a receiver and a transmitter.
    1 shows a configuration of a FIFO memory of a UART that does not support infrared communication, and requires 16 bytes of FIFO memory at the receiving end and the transmitting end, respectively.
    When the signals of Tx-RD, Tx-WR, Rx-RD, and Rx-WR input to the read and write counters (1), (2), (3) and (4) of the transmitter or the receiver are activated, the respective counters operate the counter operation. Each read and write decoder 5, 6, 7 and 8 reads or writes an address through the Tx FIFO memory section 9 or the Rx FIFO memory section 10.
    At this time, the Tx-MUX 11 for multiplexing and outputting the signals of the read decoder 5 and the write decoder 6 is configured at the above-mentioned transmitting end.
    In addition, an Rx-MUX 12 for multiplexing and outputting the signals of the read decoder 7 and the write decoder 8 is configured at the receiving end.
    In the case of the UART supporting 4 Mbps infrared communication as shown in FIG. 3, the receiver and the transmitter require 32 bytes of FIFO memory.
    When the Tx-RD signal is activated at the transmitting end, the read counter 13 performs a counter operation and reads the address to be read through the read decoder 14 through the 32-byte Tx FIFO memory unit 21.
    When the Tx-WR signal is activated, the write counter 15 performs a count operation and writes an address to be read through the write decoder 16 through the 32-byte Tx FIFO memory unit 21.
    At this time, the Tx-MUX 23 for multiplexing and outputting the signals of the read decoder 14 and the write decoder 16 is configured at the transmitting end.
    When the Rx-RD signal is activated at the receiving end, the read counter 17 performs a counter operation and reads an address to be read through the read decoder 18 through the 32-byte Rx FIFO memory unit 22.
    When the Rx-WR signal is activated, the write counter 19 performs a counter operation and writes an address to be written through the write decoder 20 through the 32-byte RX-FIFO memory unit 22.
    In this case, an Rx-MUX 24 for multiplexing and outputting signals of the read decoder 18 and the write decoder 20 is configured at the receiving end.
    In case of UART supporting infrared communication, it supports both half duplex and full duplex mode, but if it does not support infrared communication, select full duplex, and if it supports infrared communication, Select the duplex.
    In the prior art UART, 32 bytes of FIFO memory are used for a large receiver and a transmitter for supporting 4 Mbps infrared communication.
    However, since the support mode of infrared communication uses half duplex instead of full duplex, it is not necessary to use FIFO memory with 32 bytes, but the chip size is large because FIFO memory is used. .
    SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the asynchronous data transceiver of the prior art as described above, and an object thereof is to provide an asynchronous data transceiver which reduces the chip area by reducing the memory capacity.
    1 is a configuration diagram of a FIFO memory of a UART that does not support the infrared communication of the prior art, Figure 2 is a configuration diagram of a FIFO memory of the UART supporting 4Mbps infrared communication of the prior art, Figure 3 is a FIFO of the UART according to the present invention 4 is a detailed configuration diagram of the FIFO controller selection unit according to the present invention, FIG. 5 is a detailed configuration diagram of the FIFO controller according to the present invention, and FIG. 6 is an operation waveform diagram of the FIFO controller selection unit.
    Explanation of symbols for the main parts of the drawings
    40. First FIFO Memory Section 41. Second FIFO Memory Section
    42. Optional FIFO Memory Section 43. First Multiplexing / Decoding Section
    44. Second Multiplexing / Decoding Unit 45. Third Multiplexing / Decoding Unit
    46. First transmission / reception selection unit 47. Second transmission / reception selection unit
    48. First FIFO Controller Selection Section 49. Second FIFO Controller Selection Section
    50. First FIFO Controller 51. Second FIFO Controller
    52. Half Duplex Mode Controller
    The asynchronous data transmission / reception apparatus of the present invention, which supports infrared communication and reduces memory capacity, is selected and used when the first and second FIFO memories are used when the first and second FIFO memories are full, and the first and second FIFO memories are used when inputting and receiving data. Multiplexing and decoding the selected FIFO memory section, a first and second FIFO controller selection section for countering and outputting an address related to data transmission or reception, and an address counter signal of the first FIFO controller selection section in a data reception mode. A first multiplexing / decoding unit for outputting to the first FIFO memory, a second multiplexing / decoding unit for multiplexing and decoding an address count signal of the second FIFO controller selection unit in a data transmission mode and outputting the same to the second FIFO memory; When the selected FIFO memory unit is used, it is determined whether the transmission mode or the reception mode is used for each write / read operation. A first multiplexing / transmitting section for outputting an address counter signal and a third multiplexing / decoding section for multiplexing and decoding address counter signals related to read / write of the first and second transceiving selectors and outputting them to a selected FIFO memory section; It is characterized in that the configuration.
    Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the asynchronous data transmission and reception apparatus of the present invention.
    3 is a block diagram of a FIFO memory main block of a UART according to the present invention.
    The asynchronous data transceiver of the present invention for reducing the FIFO memory capacity of a UART supporting 4 Mbps infrared communication includes a first FIFO memory unit 40 having a 16-byte capacity used for receiving data input / output, and used for transmitting data input / output. A second FIFO memory section 41 having a 16-byte capacity and a selection FIFO commonly used with the first FIFO memory section 40 or the second FIFO memory section 41 at the time of selective output of data in the infrared communication mode. The memory unit 42 and the first and second FIFO memory units 40 and 41 and the selected FIFO memory unit 42 when the read signal RD and the write signal WR are generated by data transmission / reception. A first FIFO controller selector 48 and a second FIFO for counter addressing and outputting address and outputting address counter signals (WR-Sel-fifo and RD-Sel-fifo) for reading and writing data during infrared communication. Controller selector 49 and data reception mode The 16-bit address is generated by multiplexing and decoding the address counter signals WR-fifo and RD-fifo related to the read / write of the first FIFO controller selector 48 by the control signal (control-Rx). The first multiplexing / decoding unit 43 outputs to the first FIFO memory unit 40 and the control signal (control-Tx) relating to a data transmission mode of the second FIFO controller selection unit 49. The second multiplexing / decoding unit 44 which multiplexes and decodes address counter signals WR-fifo and RD-fifo related to read / write, generates 16-bit addresses, and outputs the 16-bit address to the second FIFO memory unit 41. And a write address counter signal WR-Sel-fifo relating to data transmission and reception during infrared communication by the first FIFO controller selector 48 and data transmission and reception during infrared communication by the second FIFO controller selector 49. When the write address counter signal (WR-Sel-fifo) for A first transmission / reception selection unit 46 which determines whether the transmission mode or the reception mode is determined by the reception enable signals Tx-en and Rx-en, and outputs a write address counter signal of the selection FIFO memory unit 42; And a read address counter signal RD-Sel-fifo relating to data transmission and reception during infrared communication by the first FIFO controller selector 48 and data transmission and reception during infrared communication by the second FIFO controller selector 49. When the read address counter signal RD-Sel-fifo is input, it is determined whether the transmission mode or the reception mode is determined by the transmit / receive enable signals Tx-en and Rx-en. Read / write of the first and second transmission / reception selection units 46 and 47 by a second transmission / reception selection unit 47 for outputting a read signal and a data transmission / reception selection signal (control-Sel) when supporting an infrared communication mode. Multiplex and decode the address counter signal for write to And a third multiplexing / decoding section 45 which multiplexes and decodes the address counter signal of the memory card and outputs a 16-bit address to the selection FIFO memory section 42 described above.
    The detailed configuration of the first FIFO controller selector 48 and the second FIFO controller selector 49 is as follows.
    4 is a detailed block diagram of a FIFO controller selection unit according to the present invention.
    The FIFO controller selector according to the present invention is used in full duplex mode unless the half duplex signal is enabled.
    That is, only the first and second FIFO memory units 40 and 41 are output by outputting only address counter signals WR-fifo and RD-fifo for reading / writing in a state that does not support infrared communication. When enabled, the address counter signals WR-Sel-fifo and RD-Sel-fifo for reading / writing in the infrared communication mode state are output to use the selection FIFO memory section 42 as well.
    The configuration receives read / write enable signals (WR-en, RD-en) and read / write signals (WR, RD), and outputs address counter signals (WR-fifo, RD-fifo) for reading and writing. A first FIFO controller 50 and a second FIFO controller 51 for comparing the read address counter signal with the write address counter signal and outputting a comparison signal Full 1,2 (Empty 1,2) relating to the duplex of the full or half; When the half duplex signal is enabled, the read address count signal RD-fifo of the first FIFO controller 50 and the comparison signal Impact 2 regarding the half duplex mode of the second FIFO controller 51 are compared. And multiplexing the half-duplex mode controller 52 which is latched and output to the second FIFO controller 50, and the comparison signals Full 1,2 and Empty 1,2 relating to the full or half duplex. First and second MUXs 53 output to the FIFO controller selector 48 and the second FIFO controller selector 49. It consists of 54.
    The detailed configuration of the FIFO controller is as follows.
    5 is a detailed block diagram of a FIFO controller according to the present invention.
    The FIFO controller includes a write counter 55 for outputting an address counter signal WR-fifo for writing by the read enable signal RD-en, and an address for reading with the write enable signal WR-en. A first comparator 57 for comparing the read counter 56 for outputting the counter signal RD-fifo, the MSB of the write counter 55 and the MSB of the read counter 56, and outputting a comparison value thereof; A first comparator 58 for comparing the address counter signal for writing the write counter 55 with the count signal for reading the read counter 56 and outputting a comparison value, and the first and second comparators (1) a first AND gate for performing a logic operation on the comparison value of 58 and outputting a signal related to the half duplex, the inverted comparison value of the first comparison unit 57 and the second comparison unit 58 The second AND gate outputs a signal (Full) related to the full duplex by comparing the comparison value of the .
    A detailed configuration of the half duplex mode controller 52 of the FIFO controller selection unit is as follows.
    When the signal related to the half duplex is in a deserial state by comparing the signal 2 related to the inverted half duplex of the second FIFO controller 51 with the read address counter signal RD-fifo of the second FIFO controller 50. A comparator 59 for maintaining the value when the read address count value is 15 and outputting 1 to the output, and outputting the read address counter value to the output if the signal for the half duplex is enabled; and for the half duplex The first latch unit 60, which is enabled by the signal 2 and latches and outputs a signal Full 1 related to the full duplex of the first FIFO controller 50, and the output signal of the comparison unit 59. Enabled by the second latch unit 61 for latching and outputting the output value of the latch unit 60, the signal related to the half duplex output from the system controller (not shown) and the first FIFO Maid The latch value output from the first and second gates 62 and the second latch unit 61 and the first and second gates 62 which logically calculate and output a signal Full 1 related to the full duplex of the roller 50 and the first FIFO controller 50 Logic operation of the second end gate 62 for performing logic operation on the signal Full associated with the full duplex and outputting the signals Full 1 and 2 for the full duplex of the first and second FIFO controllers 50 and 51. And an OR gate 65 for logically calculating and outputting signals 1 and 2 related to the half duplex of the first and second FIFO controllers 50 and 51. do.
    The asynchronous data transmission / reception apparatus of the present invention configured as described above outputs address counter signals related to reading and writing from the first and second FIFO controllers 50 and 51, compares MSBs of the counter values, and compares the counter values. Outputs a signal regarding full or half duplex mode.
    By the above logic, the data transmission / reception operation supported by the 32-byte receive FIFO memory and the 32-byte transmit FIFO memory can be supported by three 16-byte FIFO memories.
    That is, in the data transmission / reception operation, if the first and second FIFO memory sections 40 and 41 are not completely full, the data transmission / reception operation is performed using only the first and second FIFO memory sections 40 and 41. When the first and second FIFO memory units 40 and 41 are completely full, the data transmission / reception operation is further performed using the selection FIFO memory unit 42.
    The generation of logic for selecting the first and second FIFO memory sections 40 and 41 and the selection FIFO memory section 42 is performed by the first and second FIFO controller selection sections 48 and 49.
    The operation waveforms of the first and second FIFO controller selectors 48 and 49 are as shown in FIG. 6.
    The operation of the asynchronous data transceiver of the present invention will be described in detail as follows.
    When the asynchronous data transceiver is in the full duplex mode (not the infrared communication mode), the half duplex mode is in a deactivated state, and data is generated using only the 16-byte first and second FIFO memory units 40 and 41. Send and receive operation.
    In this state, when the half duplex mode is enabled, the Full 1 signal of the first FIFO controller 50 is enabled, and the write address count is performed by the second FIFO controller 51 by the latch signals of the first and second latch units 60 and 61. Will generate a signal.
    By using the logic of the first and second FIFO controller selection unit 48 and 49 as described above, one of the first and second FIFO memory units 40 and 41 and the selected FIFO memory unit 42 are selected to transmit and receive data. It will work.
    When the selection FIFO memory unit 42 is selected, the first and second transmission / reception selection units 46 and 47 transmit or transmit the signal by the transmit enable signal Tx-en and the receive enable signal Rx-en. Choose whether to receive mode to write and read data.
    In this case, since the UART of the present invention is in the half duplex mode (that is, the infrared communication mode), the transmit enable signal and the receive enable signal are not simultaneously enabled.
    In the UART of the present invention, the full duplex mode and the half duplex mode (infrared communication are supported) are divided into 16 bytes of FIFO memory and an infrared communication mode, that is, the FIFO memory of the transceiver is full. When 16 bytes of selected FIFO memory is selected and used, data can be transmitted and received.
    Therefore, it is possible to reduce the chip size of the data transceiver by allowing data to be read and written at a high data transfer rate of 4 Mbps with low memory capacity.
    权利要求:
    Claims (9)
    [1" claim-type="Currently amended] The first and second FIFO memory units used for input and output of data transmitted and received, the selected FIFO memory unit selected and used when the first and second FIFO memories are full, and an address relating to the transmission or reception of data A first multiplexer / decoder for outputting the first and second FIFO controller selectors, a first multiplexer / decoder for multiplexing and decoding the address counter signal of the first FIFO controller selector in a data reception mode, and outputting the data to a first FIFO memory; A second multiplexing / decoding section for multiplexing and decoding the address counter signal of the second FIFO controller selecting section and outputting the same to the second FIFO memory, and determining whether the transmission mode or the receiving mode is used when the selected FIFO memory section is used. First and second transmission / reception selection units for outputting a write / read address counter signal, and reading of the first and second transmission / reception selection units / Writing the asynchronous data transmitting and receiving device characterized in that the configuration comprises a third multiplexer / decoding for multiplexing and decoding to output to the selected FIFO memory, the address counter signal on.
    [2" claim-type="Currently amended] 2. The asynchronous data transmitting / receiving apparatus according to claim 1, wherein the first, second FIFO memory unit and the selected FIFO memory unit each have a capacity of 16 bytes.
    [3" claim-type="Currently amended] The asynchronous data transmission / reception apparatus according to claim 1, wherein the first, second, and third multiplexing / decoding sections output 16-bit addresses, respectively.
    [4" claim-type="Currently amended] The asynchronous data transmission / reception apparatus according to claim 1, wherein the first and second transmission / reception selection units do not enable the transmission mode and the reception mode at the same time.
    [5" claim-type="Currently amended] The apparatus of claim 1, wherein the first and second FIFO controller selectors support a full duplex mode when the half duplex signal is not enabled.
    [6" claim-type="Currently amended] The memory device of claim 5, wherein the first and second FIFO controller selectors output only the address counter signals WR-fifo and RD-fifo related to read / write and not the infrared communication mode in the full duplex mode. When the half duplex signal is enabled, it outputs the address counter signal (WR-Sel-fifo, RD-Sel-fifo) related to read / write in the infrared communication mode state, and also uses the selected FIFO memory unit. Asynchronous data transmission and reception device characterized in that the transmission and reception of data.
    [7" claim-type="Currently amended] The read / write enable signals WR-en and RD-en and the read / write signals WR and RD of the first 2FIFO controller selector respectively receive read and write address counter signals WR-. a first FIFO controller that outputs fifo, RD-fifo, and compares the read address counter signal with the write address counter signal and outputs a comparison signal (Full 1,2) (Empty 1,2) relating to the duplex of the full or half (50) When the second FIFO controller and the half duplex signal are enabled, the comparison signal (Empty 2) regarding the read address counter signal RD-fifo of the first FIFO controller and the half duplex mode of the second FIFO controller is supplied. A half duplex mode controller which compares, latches, and outputs the second FIFO controller to the second FIFO controller; and a first FIFO controller selector by multiplexing the comparison signals (Full 1,2) (Empty 1,2) for the full or half duplex. Output to the second FIFO controller selector The asynchronous data transmitting and receiving device, characterized in that consisting of the 1,2 MUX.
    [8" claim-type="Currently amended] The write counter of claim 7, wherein each of the first and second FIFO controllers outputs an address counter signal WR-fifo related to writing by a read enable signal RD-en, and a write enable signal WR-. en) a read counter for outputting an address counter signal RD-fifo for reading, a first comparison unit for comparing the MSB of the write counter with the MSB of the read counter and outputting a comparison value thereof, and the write counter A first comparison unit for comparing an address counter signal for writing a signal with a count signal for reading a read counter and outputting a comparison value; and a signal for a half duplex by performing a logical operation on a comparison value of the first and second comparison units. Empty) and a second AND gate for outputting a signal (Full) for the full duplex by comparing the inverted comparison value of the first comparator and the comparison value of the second comparator, characterized in that Ha Is an asynchronous data transceiver.
    [9" claim-type="Currently amended] The half-duplex mode controller of claim 6, wherein the half-duplex mode controller compares the signal (Empty 2) of the inverted half-duplex of the second FIFO controller with the read address counter signal (RD-fifo) of the second FIFO controller. When the read address counter value is 15 and the read address counter value is 15, the value is continuously maintained and 1 is outputted. When the signal related to the half duplex is enabled, the comparison unit outputs the read address counter value to the output. The first latch unit is enabled by the signal (Empty 2) and latches and outputs a signal (Full 1) related to the full duplex of the first FIFO controller, and is enabled by the output signal of the comparator unit. A second latch unit for latching and outputting an output value of the first latch unit, a signal related to a half duplex, and a full duplex of the first FIFO controller A first AND gate performing a logic operation on the signal Full 1, a second latch logic outputting a latch value output from the second latch unit, and a signal Full regarding the full duplex of the first FIFO controller. An AND gate, a third end gate for performing a logic operation on the full duplex signals of the first and second FIFO controllers (Full 1 and 2), and a signal related to the half duplex of the first and second FIFO controllers (Empty 1, 2) an asynchronous data transceiver comprising a OR gate for outputting a logical operation.
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    同族专利:
    公开号 | 公开日
    KR100210031B1|1999-07-15|
    JPH10222442A|1998-08-21|
    TW341683B|1998-10-01|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1996-12-31|Application filed by 문정환, 엘지반도체 주식회사
    1996-12-31|Priority to KR1019960079242A
    1998-10-07|Publication of KR19980059896A
    1999-07-15|Application granted
    1999-07-15|Publication of KR100210031B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019960079242A|KR100210031B1|1996-12-31|1996-12-31|Asynchronous data transmit/receive apparatus|
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